A 25Gb/s 170μW/Gb/s Optical Receiver in 28nm CMOS for Chip-to-Chip Optical Communication

A low-power high-speed optical receiver in 28nm CMOS is presented. The design features a novel architecture combining a low-bandwidth TIA front-end, double-sampling technique and dynamic offset modulation. The low-bandwidth TIA increases receiver’s sensitivity while adding minimal power overhead. Functionality of the receiver was validated and the design is compared with a conventional 3-stage TIA receiver via actual measurements. The proposed receiver architecture achieves error-free operation (BER<10) at 25Gb/s with energy efficiency of 170fJ/b while the conventional receiver achieves error-free operation at 17.1Gb/s with energy efficiency of 260fJ/b. Index Terms — high-speed transceivers, hybrid integrated circuits, optical interconnection, sampled-data circuits.